305 search results - page 49 / 61 » On modeling top-down VLSI design |
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...