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» On modeling top-down VLSI design
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GLVLSI
2003
IEEE
144views VLSI» more  GLVLSI 2003»
14 years 22 days ago
A hybrid adiabatic content addressable memory for ultra low-power applications
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...
Aiyappan Natarajan, David Jasinski, Wayne Burleson...
DAC
2006
ACM
14 years 8 months ago
Circuit simulation based obstacle-aware Steiner routing
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing t...
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
14 years 7 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
FCCM
2009
IEEE
121views VLSI» more  FCCM 2009»
14 years 2 months ago
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy
—Photodynamic therapy (PDT) is a method of treating cancer that combines light and light-sensitive drugs to selectively destroy cancerous tumours without harming the healthy tiss...
Jason Luu, Keith Redmond, William Lo, Paul Chow, L...
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
14 years 1 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...