305 search results - page 7 / 61 » On modeling top-down VLSI design |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ICPP
1987
IEEE
13 years 11 months ago
1987
IEEE
Abstract. We address the problem of designing and building efficient custom Vl.Sl-besed processors to do computations on large multi-dimensional lattices. The design tradeoffs for ...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
ICPP
2000
IEEE
14 years 17 hour ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
ISPD
1999
ACM
13 years 12 months ago
1999
ACM
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...