Sciweavers

140 search results - page 11 / 28
» On multiple-voltage high-level synthesis using algorithmic t...
Sort
View
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 3 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 9 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ICIP
2007
IEEE
13 years 10 months ago
Bayesian Example Based Segmentation using a Hybrid Energy Model
This paper describes a supervised segmentation algorithm which draws inspiration from recent advances in non-parametric texture synthesis. A set of example images which have been ...
Claire Gallagher, Anil C. Kokaram
DATE
2005
IEEE
124views Hardware» more  DATE 2005»
14 years 2 months ago
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
Raoul F. Badaoui, Ranga Vemuri