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» On optimal input design in system identification for control
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LCTRTS
2007
Springer
14 years 3 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
TVLSI
1998
122views more  TVLSI 1998»
13 years 8 months ago
Algorithm-based low-power transform coding architectures: the multirate approach
—In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes...
An-Yeu Wu, K. J. Ray Liu
DAC
2001
ACM
14 years 10 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
MOBICOM
2005
ACM
14 years 2 months ago
Challenges: communication through silence in wireless sensor networks
Wireless sensor networks (WSNs) are typically characterized by a limited energy supply at sensor nodes. Hence, energy efficiency is an important issue in the system design and op...
Yujie Zhu, Raghupathy Sivakumar
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
14 years 1 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...