46 search results - page 8 / 10 » On pipelining dynamic instruction scheduling logic |
CF
2011
ACM
12 years 7 months ago
2011
ACM
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...