37 search results - page 3 / 8 » On power and fault-tolerance optimization in FPGA physical s... |
FPL
2005
Springer
14 years 3 months ago
2005
Springer
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
EMSOFT
2011
Springer
12 years 9 months ago
2011
Springer
Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective a...
ICCAD
2007
IEEE
14 years 6 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...