Sciweavers

66 search results - page 9 / 14
» On reducing misspeculations in a pipelined scheduler
Sort
View
ICC
2007
IEEE
121views Communications» more  ICC 2007»
14 years 4 months ago
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches
– Optical burst switching (OBS) is a promising technique for next-generation optical switching networks. In traditional OBS, an entire burst is discarded when all output waveleng...
Muhammad T. Anan, Ghulam Chaudhry
ICCAD
2001
IEEE
126views Hardware» more  ICCAD 2001»
14 years 6 months ago
Constraint Satisfaction for Relative Location Assignment and Scheduling
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Je...
CGO
2004
IEEE
14 years 1 months ago
Probabilistic Predicate-Aware Modulo Scheduling
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
13 years 1 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
HPCA
2006
IEEE
14 years 10 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...