166 search results - page 18 / 34 » On testing delay faults in macro-based combinational circuit... |
AICCSA
2006
IEEE
13 years 9 months ago
2006
IEEE
To excite a stuck-open fault in a CMOS combinational circuit, it is only necessary that the output of the gate containing the fault takes on opposite values during the application...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...