418 search results - page 15 / 84 » On the Adders with Minimum Tests |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
JCO
2007
13 years 7 months ago
2007
This paper discusses the relation among four problems: graph testing, DNA complex screening, superimposed codes and secure key distribution. We prove a surprising equivalence relat...
FOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
—We introduce a new tool for approximation and testing algorithms called partitioning oracles. We develop methods for constructing them for any class of bounded-degree graphs wit...