418 search results - page 2 / 84 » On the Adders with Minimum Tests |
ISLPED
2007
ACM
13 years 8 months ago
2007
ACM
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
EUROGP
2000
Springer
13 years 10 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...