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» On the Complexity of Circuit Satisfiability
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ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
14 years 2 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
DATE
1998
IEEE
141views Hardware» more  DATE 1998»
14 years 2 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
ITC
1998
IEEE
94views Hardware» more  ITC 1998»
14 years 2 months ago
Testing embedded-core based system chips
Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from scratch and reuse...
Yervant Zorian, Erik Jan Marinissen, Sujit Dey
ISLPED
1998
ACM
78views Hardware» more  ISLPED 1998»
14 years 2 months ago
Power-delay tradeoffs for radix-4 and radix-8 dividers
The use of higher radices in division reduces the number of iterations to complete the operation, but increases the complexity of the circuit. In this paper we explore the in uenc...
Alberto Nannarelli, Tomás Lang
CTRSA
2009
Springer
106views Cryptology» more  CTRSA 2009»
14 years 2 months ago
Communication-Efficient Private Protocols for Longest Common Subsequence
We design communication efficient two-party and multi-party protocols for the longest common subsequence (LCS) and related problems. Our protocols achieve privacy with respect to p...
Matthew K. Franklin, Mark Gondree, Payman Mohassel