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» On the Complexity of Circuit Satisfiability
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CDC
2009
IEEE
122views Control Systems» more  CDC 2009»
13 years 6 months ago
Reduced complexity models in the identification of dynamical networks: Links with sparsification problems
In many applicative scenarios it is important to derive information about the topology and the internal connections of more dynamical systems interacting together. Examples can be ...
Donatello Materassi, Giacomo Innocenti, Laura Giar...
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
14 years 1 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ICCAD
1997
IEEE
99views Hardware» more  ICCAD 1997»
14 years 29 days ago
High-level area and power estimation for VLSI circuits
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
Mahadevamurty Nemani, Farid N. Najm
VLSID
1997
IEEE
135views VLSI» more  VLSID 1997»
14 years 28 days ago
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
ASPDAC
1998
ACM
65views Hardware» more  ASPDAC 1998»
14 years 29 days ago
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
Miyako Tandai, Takao Shinsha