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» On the Complexity of Register Coalescing
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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
13 years 12 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
13 years 12 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 12 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
SIGGRAPH
1999
ACM
13 years 12 months ago
A Morphable Model for the Synthesis of 3D Faces
In this paper, a new technique for modeling textured 3D faces is introduced. 3D faces can either be generated automatically from one or more photographs, or modeled directly throu...
Volker Blanz, Thomas Vetter
ICCAD
1999
IEEE
90views Hardware» more  ICCAD 1999»
13 years 12 months ago
Marsh: min-area retiming with setup and hold constraints
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...