Sciweavers

129 search results - page 15 / 26
» On the Computational Power of Threshold Circuits with Sparse...
Sort
View
DAC
2005
ACM
13 years 9 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
MOBICOM
2012
ACM
11 years 10 months ago
Faster GPS via the sparse fourier transform
GPS is one of the most widely used wireless systems. A GPS receiver has to lock on the satellite signals to calculate its position. The process of locking on the satellites is qui...
Haitham Hassanieh, Fadel Adib, Dina Katabi, Piotr ...
ICIP
2010
IEEE
13 years 5 months ago
Metaface learning for sparse representation based face recognition
Face recognition (FR) is an active yet challenging topic in computer vision applications. As a powerful tool to represent high dimensional data, recently sparse representation bas...
Meng Yang, Lei Zhang, Jian Yang, David Zhang
DAC
2005
ACM
14 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
DAC
2004
ACM
14 years 8 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...