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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 17 days ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
DAC
2006
ACM
14 years 8 months ago
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
Hao Yu, Yiyu Shi, Lei He
ISCAS
2003
IEEE
98views Hardware» more  ISCAS 2003»
14 years 28 days ago
Dynamic operand transformation for low-power multiplier-accumulator design
: The design of portable battery-operated devices requires low-power computation circuits. This paper presents a new multiplier-accumulator (MAC) design approach, which in contrast...
Masayoshi Fujino, Vasily G. Moshnyaga
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
14 years 4 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
DAC
2006
ACM
14 years 8 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm