Abstract. Consider a weighted and undirected graph, possibly with self-loops, and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements correspon...
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...