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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 8 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
DATE
2006
IEEE
116views Hardware» more  DATE 2006»
14 years 1 months ago
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
DAC
2007
ACM
13 years 11 months ago
Side-Channel Attack Pitfalls
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
Kris Tiri
IEEESCC
2005
IEEE
14 years 1 months ago
Web Services Composition: A Story of Models, Automata, and Logics
eal world”, represented abstractly using (time-varying) first-order logic predicates and terms. A representative composition result [11] here uses a translation into Petri nets. ...
Richard Hull
EDCC
1999
Springer
13 years 11 months ago
Dependability Modelling and Sensitivity Analysis of Scheduled Maintenance Systems
Abstract. In this paper we present a new modelling approach for dependability evaluation and sensitivity analysis of Scheduled Maintenance Systems, based on a Deterministic and Sto...
Andrea Bondavalli, Ivan Mura, Kishor S. Trivedi