372 search results - page 37 / 75 » On the Fault Testing for Reversible Circuits |
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
VTS
2002
IEEE
14 years 14 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
VTS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...