372 search results - page 68 / 75 » On the Fault Testing for Reversible Circuits |
WISES
2004
13 years 8 months ago
2004
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
DFT
1999
IEEE
13 years 11 months ago
1999
IEEE
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...