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» On the Fault Testing for Reversible Circuits
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VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 7 months ago
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...
FDL
2007
IEEE
14 years 1 months ago
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
Daniel Große, Hernan Peraza, Wolfgang Klinga...
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
13 years 11 months ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
ICCAD
2005
IEEE
105views Hardware» more  ICCAD 2005»
14 years 4 months ago
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Cha...
DAC
2006
ACM
14 years 8 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...