Sciweavers

340 search results - page 45 / 68
» On the Interplay of Parallelization, Program Performance, an...
Sort
View
ICS
2000
Tsinghua U.
14 years 1 days ago
A low-complexity issue logic
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
Ramon Canal, Antonio González
EMSOFT
2005
Springer
14 years 2 months ago
AutoDVS: an automatic, general-purpose, dynamic clock scheduling system for hand-held devices
We present AutoDVS, a dynamic voltage scaling (DVS) system for hand-held computers. Unlike extant DVS systems, AutoDVS distinguishes common, course-grain, program behavior and cou...
Selim Gurun, Chandra Krintz
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 2 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
PLDI
2005
ACM
14 years 2 months ago
Programming ad-hoc networks of mobile and resource-constrained devices
Ad-hoc networks of mobile devices such as smart phones and PDAs represent a new and exciting distributed system architecture. Building distributed applications on such an architec...
Yang Ni, Ulrich Kremer, Adrian Stere, Liviu Iftode
ICDE
2010
IEEE
248views Database» more  ICDE 2010»
14 years 8 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...