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» On the Limits of Leakage Power Reduction in Caches
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ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
14 years 1 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
ICCAD
2006
IEEE
107views Hardware» more  ICCAD 2006»
14 years 4 months ago
Decoupling capacitor planning and sizing for noise and leakage reduction
—Decoupling capacitors (decaps) are a popular means for reducing power-supply noise in integrated circuits. Since the decaps are usually inserted in the whitespace of the device ...
Eric Wong, Jacob R. Minz, Sung Kyu Lim
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
13 years 5 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
TVLSI
2008
153views more  TVLSI 2008»
13 years 7 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 11 days ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...