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» On the Masking Countermeasure and Higher-Order Power Analysi...
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ESAS
2004
Springer
14 years 26 days ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko
CHES
2008
Springer
146views Cryptology» more  CHES 2008»
13 years 9 months ago
Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration
Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead...
Nele Mentens, Benedikt Gierlichs, Ingrid Verbauwhe...
FPL
2006
Springer
219views Hardware» more  FPL 2006»
13 years 11 months ago
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
François-Xavier Standaert, Gaël Rouvro...
CODES
2007
IEEE
14 years 1 months ago
A smart random code injection to mask power analysis based side channel attacks
One of the security issues in embedded system is the ability of an adversary to perform side channel attacks. Power analysis attacks are often very successful, where the power seq...
Jude Angelo Ambrose, Roshan G. Ragel, Sri Paramesw...
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
13 years 11 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki