Abstract. A digit-serial, multiplier-accumulator based cryptographic coprocessor architecture is proposed, similar to fix-point DSP's with enhancements, supporting long modula...
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
To accomplish frequent, simple tasks with high efficiency, it is necessary to leverage low-power, microcontroller-like processors that are increasingly available on mobile systems...
Felix Xiaozhu Lin, Zhen Wang, Robert LiKamWa, Lin ...
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
Federico Angiolini, Francesco Menichelli, Alberto ...
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...