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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
SIGGRAPH
2000
ACM
14 years 2 days ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
13 years 8 months ago
Computing robustness of FlexRay schedules to uncertainties in design parameters
Abstract--In the current environment of rapidly changing invehicle requirements and ever-increasing functional content for automotive EE systems, there are several sources of uncer...
Arkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 8 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
AINA
2007
IEEE
13 years 11 months ago
On the Design of an Efficient Architecture for Supporting Large Crowds of Autonomous Agents
Crowd simulations require both rendering visually plausible images and managing the behavior of autonomous agents. Therefore, these applications need an efficient design that allo...
Miguel Lozano, Pedro Morillo, Juan M. Orduñ...