Sciweavers

305 search results - page 15 / 61
» On the Power of Networks of Evolutionary Processors
Sort
View
LCN
2005
IEEE
14 years 1 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
IPPS
2007
IEEE
14 years 1 months ago
Peak-Performance DFA-based String Matching on the Cell Processor
The security of your data and of your network is in the hands of intrusion detection systems, virus scanners and spam filters, which are all critically based on string matching. ...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...
CSE
2009
IEEE
14 years 2 months ago
Prospector: Multiscale Energy Measurement of Networked Embedded Systems with Wideband Power Signals
Abstract—Today’s wirelessly networked embedded systems underlie a vast array of electronic devices, performing computation, communication, and input/output. A major design goal...
Kenji R. Yamamoto, Paul G. Flikkema
HPCA
2003
IEEE
14 years 8 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 1 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...