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ESA
2001
Springer
75views Algorithms» more  ESA 2001»
14 years 6 days ago
Strongly Competitive Algorithms for Caching with Pipelined Prefetching
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
Alexander Gaysinsky, Alon Itai, Hadas Shachnai
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 2 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
CF
2010
ACM
14 years 24 days ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...
ISCA
2006
IEEE
148views Hardware» more  ISCA 2006»
14 years 1 months ago
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 2 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...