In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
Stephen Friedman, Allan Carroll, Brian Van Essen, ...