415 search results - page 22 / 83 » On the energy-efficiency of speculative hardware |
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ISLPED
2009
ACM
14 years 4 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
ISCA
2006
IEEE
14 years 4 months ago
2006
IEEE
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
ISCA
2000
IEEE
14 years 2 months ago
2000
IEEE
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
ICCD
2002
IEEE
14 years 6 months ago
2002
IEEE
This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectivel...