415 search results - page 33 / 83 » On the energy-efficiency of speculative hardware |
ICCD
2007
IEEE
14 years 25 days ago
2007
IEEE
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
Energy dissipation from the issue queue and register file constitutes a large portion of the overall energy budget of an aggressive dynamically scheduled microprocessor. We propo...
SBACPAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper presents an in-depth case study in highperformance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rai...
MICRO
2000
IEEE
14 years 1 months ago
2000
IEEE
Current superscalar microprocessors’ performance depends on its frequency and the number of useful instructions that can be processed per cycle (IPC). In this paper we propose a...