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» On the energy-efficiency of speculative hardware
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ASPLOS
2006
ACM
14 years 1 months ago
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkate...
WCAE
2006
ACM
14 years 1 months ago
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis
Two of the most important design issues for modern processors are power and performance. It is important for students in computer organization classes to understand the tradeoff b...
Clint W. Smullen, Tarek M. Taha
EUROPAR
2005
Springer
14 years 1 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
14 years 27 days ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...
ICCD
2000
IEEE
80views Hardware» more  ICCD 2000»
14 years 1 days ago
Power-Sensitive Multithreaded Architecture
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...
John S. Seng, Dean M. Tullsen, George Cai