415 search results - page 70 / 83 » On the energy-efficiency of speculative hardware |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
ACSAC
2003
IEEE
14 years 28 days ago
2003
IEEE
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
MICRO
2003
IEEE
14 years 27 days ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...