415 search results - page 7 / 83 » On the energy-efficiency of speculative hardware |
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
- Real-time scheduling on processors that support dynamic voltage and frequency scaling is analyzed. The Slacked Earliest Deadling First (SEDF) algorithm is proposed and it is show...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...