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» On two-step routing for FPGAS
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ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
14 years 3 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm
FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
13 years 11 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
13 years 11 months ago
Satisfiability-Based Detailed FPGA Routing
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
FPL
2008
Springer
138views Hardware» more  FPL 2008»
13 years 8 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
FPL
2003
Springer
109views Hardware» more  FPL 2003»
13 years 12 months ago
Globally Asynchronous Locally Synchronous FPGA Architectures
Abstract. Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchron...
Andrew Royal, Peter Y. K. Cheung