11 search results - page 2 / 3 » On-Chip Jitter Measurement for Phase Locked Loops |
ISCAS
2002
IEEE
14 years 11 days ago
2002
IEEE
This paper presents a method for analyzing the Bit Error Rate of recovered data for PLL-based data recovery systems (DRS) as the PLL comes into lock. This method is based on the a...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes applications such as the Serial AT Attachment. The proposed design co...
ITC
2003
IEEE
14 years 22 days ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
We propose to include synchrony effects, known to exist in the auditory system, to represent voiced parts of the speech signal in a robust way. The system decomposes the input sig...