45 search results - page 3 / 9 » On-chip implementation of multiprocessor networks and switch... |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...