704 search results - page 3 / 141 » On-chip logic minimization |
ARC
2007
Springer
14 years 4 months ago
2007
Springer
Abstract. In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identic...
DAC
2001
ACM
14 years 10 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ETS
2006
IEEE
14 years 3 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
ICES
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...