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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
IJCSS
2007
133views more  IJCSS 2007»
13 years 7 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
13 years 11 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 4 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
NIPS
1998
13 years 9 months ago
Example-Based Image Synthesis of Articulated Figures
We present a method for learning complex appearance mappings, such as occur with images of articulated objects. Traditional interpolation networks fail on this case since appearan...
Trevor Darrell