54 search results - page 5 / 11 » Optimal Clock Period for Synthesized Data Paths |
VLSID
2000
IEEE
14 years 29 days ago
2000
IEEE
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
DAC
1999
ACM
14 years 27 days ago
1999
ACM
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
VLSI
2005
Springer
14 years 2 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
ICCD
1995
IEEE
14 years 4 days ago
1995
IEEE
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...