261 search results - page 15 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ASPDAC
1998
ACM
14 years 28 days ago
1998
ACM
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
ASPDAC
1998
ACM
14 years 28 days ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
ICCAD
1998
IEEE
14 years 29 days ago
1998
IEEE
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
VTS
1998
IEEE
14 years 28 days ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
VTS
1995
IEEE
14 years 7 days ago
1995
IEEE
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...