261 search results - page 33 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
FPL
2008
Springer
13 years 10 months ago
2008
Springer
This paper presents a new approach for mapping task graphs to heterogeneous hardware/software computing systems using heuristic search techniques. Two techniques: (1) integration ...
ISPD
1998
ACM
14 years 29 days ago
1998
ACM
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
ICRA
2009
IEEE
13 years 6 months ago
2009
IEEE
We aim at merging technologies from information technology, roomware, and robotics in order to design adaptive and intelligent furniture. This paper presents design principles for ...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...