261 search results - page 34 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ASPDAC
2009
ACM
14 years 22 days ago
2009
ACM
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
IOLTS
2008
IEEE
14 years 3 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
FCCM
2011
IEEE
13 years 14 days ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
CAV
2012
Springer
11 years 11 months ago
2012
Springer
Craig interpolation is a well known method of abstraction successfully used in both hardware and software model checking. The logical strength of interpolants can affect the quali...