261 search results - page 39 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
SPAA
1993
ACM
13 years 11 months ago
1993
ACM
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
ICCAD
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...