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» Optimal Hardware Pattern Generation for Functional BIST
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SAT
2009
Springer
126views Hardware» more  SAT 2009»
14 years 2 months ago
Extending SAT Solvers to Cryptographic Problems
Cryptography ensures the confidentiality and authenticity of information but often relies on unproven assumptions. SAT solvers are a powerful tool to test the hardness of certain ...
Mate Soos, Karsten Nohl, Claude Castelluccia
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
13 years 12 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
ICCD
2006
IEEE
134views Hardware» more  ICCD 2006»
14 years 1 months ago
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...
Krishnendu Chakrabarty
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 1 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 29 days ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...