261 search results - page 43 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ETS
2010
IEEE
13 years 8 months ago
2010
IEEE
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
ICCAD
2003
IEEE
14 years 25 days ago
2003
IEEE
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
JSS
2007
13 years 7 months ago
2007
A control flow trace captures the complete sequence of dynamically executed basic blocks and function calls. It is usually of very large size and therefore commonly stored in com...