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MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 1 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
MIDDLEWARE
2007
Springer
14 years 1 months ago
A piggybacking approach to reduce overhead in sensor network gossiping
Many wireless sensor network protocols are employing gossipbased message dissemination, where nodes probabilistically forward messages, to reduce message overhead. We are concerne...
Ercan Ucan, Nathanael Thompson, Indranil Gupta
IEEEPACT
2009
IEEE
14 years 2 months ago
Analytical Modeling of Pipeline Parallelism
Parallel programming is a requirement in the multi-core era. One of the most promising techniques to make parallel programming available for the general users is the use of parall...
Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Ca...
RTCSA
2008
IEEE
14 years 1 months ago
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
Cache partitioning techniques have been proposed in the past as a solution for the cache interference problem. Due to qualitative differences with general purpose platforms, real-...
Bach Duy Bui, Marco Caccamo, Lui Sha, Joseph Marti...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 20 days ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan