166 search results - page 5 / 34 » Optimal System-on-Chip Test Scheduling |
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
DATE
2002
IEEE
14 years 11 days ago
2002
IEEE
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
CL
2000
Springer
13 years 11 months ago
2000
Springer
We use Kleene algebra with tests to verify a wide assortment of common compiler optimizations, including dead code elimination, common subexpression elimination, copy propagation,...
CP
2001
Springer
13 years 12 months ago
2001
Springer
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. The local instruction scheduling problem is to nd a m...