402 search results - page 32 / 81 » Optimal clock synchronization in networks |
SIAMADS
2010
13 years 2 months ago
2010
Previous numerical and analytical work has shown that synaptic coupling can allow a network of model neurons to synchronize despite heterogeneity in intrinsic parameter values. In ...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell e...
MDM
2010
Springer
14 years 14 days ago
2010
Springer
—Current smartphones have a storage capacity of several gigabytes. More and more information is stored on mobile devices. To meet the challenge of information organization, we tu...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...