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» Optimal instruction scheduling using integer programming
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ICCAD
2004
IEEE
124views Hardware» more  ICCAD 2004»
14 years 6 months ago
Architectural-level synthesis of digital microfluidics-based biochips
Microfluidics-based biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques f...
Fei Su, Krishnendu Chakrabarty
ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
14 years 2 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
DAC
2002
ACM
14 years 10 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
14 years 2 months ago
Execution Characteristics of Desktop Applications on Windows NT
This paper examines the performance of desktop applications running on the Microsoft Windows NT operating system on Intel x86 processors, and contrasts these applications to the p...
Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Th...
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
14 years 3 months ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...